The manufacture of an integrated circuit in a semiconductor device involves the formation of a metal layer which is overlaid on another conductive layer to form a wiring pattern. This process is usually repeated several times to produce a stack of metal layers. Metal interconnects which form horizontal and vertical electrical pathways in the device are separated by dielectric layers to prevent crosstalk between the metal wiring that can degrade device performance by slowing circuit speed.
A popular method of making an interconnect structure is a damascene process in which an opening is formed in a stack of dielectric layers. In a single damascene scheme, the opening which is a via, contact hole, or a trench is lined with a diffusion barrier layer and is filled with a metal. For a dual damascene process, a via and a trench are formed in a stack of dielectric layers, lined with a diffusion barrier layer, and are simultaneously filled with metal. The most frequently used dual damascene approach is a via first process in which a via is fabricated and then a trench is formed above the via. Recent improvements in damascene processing include lowering the resistivity of the metal interconnect by switching from aluminum to copper as the metal layer and reducing the dielectric constant (k) of dielectric materials to minimize capacitance coupling between the metal interconnects. Conventional dielectric materials such as SiO2 have a k value of about 4 or larger but new technologies require a k value of below 3.5 and preferably less than 3.
One of the more promising low k dielectric materials is organosilicate glass (OSG) also known as SiCO which is oxygen doped silicon carbide. When SiCO has a significant hydrogen content, it is also referred to as SiCOH which is available as Black Diamond™ from Applied Materials, CORAL™ from Novellus, or can be obtained by different trade names from other manufacturers. For example, Black Diamond has been analyzed by RBS (Rutherford Back Scattering) to have a composition of about 20 atomic weight % silicon, about 30 at. wt. % oxygen, about 9 at. wt. % carbon, and about 36 at. wt. % hydrogen. SiCOH has a k value between about 2 and 3 and thereby provides a much needed reduction in capacitance coupling between wiring. The composition and properties of SiCOH may vary depending on deposition conditions and source gases. Typically, a silane and an oxidizing gas are flowed into a heated process chamber where a chemical vapor deposition (CVD) or a plasma enhanced CVD (PECVD) process occurs. Optionally, a single precursor may function as the silicon, carbon/hydrogen, and oxygen source gas and is usually assisted into the process chamber with an inert carrier gas.
One concern with a SiCOH dielectric layer in a damascene scheme is that the layer is porous even after heating to a temperature of 500° C. or more. A porous structure will allow moisture uptake which increases the dielectric constant and defeats the purpose of depositing a low k dielectric layer. Therefore, post-deposition treatments are frequently performed to densify the SiCOH layer and stabilize its properties during subsequent processing. A well known method of densifying a SiCOH layer is to use a plasma treatment such as the N2/NH3 plasma process found in U.S. Pat. No. 6,436,808. Besides stabilizing the dielectric constant, densification also improves SiCOH resistance to etchants such as O2 plasma during removal of a photoresist mask that is used to transfer a trench pattern into the damascene stack.
Silicon nitride or silicon carbide (SiC) are commonly employed as a barrier or etch stop layer in a damascene process. For example, a stack of dielectric layers that includes a low k dielectric layer on a SiC etch stop layer is formed on substrate that may have an exposed metal layer. However, the advantage of a low k dielectric layer is partially offset by a relatively high k value for a SiC or silicon nitride etch stop layer.
A compromise solution is reached in a prior art method depicted in FIG. 1. A substrate 1 is provided that contains a first metal layer 2 which may be adjoined on its sides and bottom by a diffusion barrier layer (not shown). An etch stop layer 3 such as SiC or silicon nitride and a low k dielectric layer 4 are sequentially formed on substrate 1. Conventional methods are used to form vias 5a, 5b in a first low k dielectric layer 4 and in etch stop layer 3 that are aligned above the first metal layer 2. The vias are lined with a diffusion barrier layer 6 and filled with a second metal layer 7 which is planarized to be coplanar with the first low k dielectric layer 4. As a first step in a damascene process to form the next metal layer, a thin (20–50 Angstrom thick) SiC layer 8 is deposited on the first low k dielectric layer 4 followed by deposition of a SiCOH layer 9 with a thickness of about 550 Angstroms. Although the composite etch stop layer comprised of SiC layer 8 and SiCOH layer 9 provides a lower dielectric constant than SiC only, the formation of the SiC layer has a low throughput because of a low deposition rate of about 1 Angstrom/sec. Furthermore, large process instability is observed due to SiC thickness variations that result in poor wafer to wafer and within wafer reliability control.
Referring to FIG. 2, a second low k dielectric layer 10 is deposited on SiCOH layer 9. Conventional methods are employed to form openings 11a, 11b in the second low k dielectric layer 10 that extend through SiCOH layer 9 and SiC layer 8 above vias 5a, 5b. A diffusion barrier layer 12 that is Ta, for example, is deposited on the sidewalls and bottom of openings 11a, 11b. A metal such as copper is deposited to fill openings 11a, 11b to form a third metal layer 13 that is subsequently planarized to be coplanar with the second low k dielectric layer 10.
An alternative barrier layer which is hydrogenated SiC is described in U.S. Pat. No. 6,541,367. In one example, the SiCH layer serves as an etch stop and a nano-porous SiO2 dielectric layer is deposited on the SiCH layer. Although an amorphous SiCH film has a lower dielectric constant (k˜4.5) than silicon nitride (k˜7), α-SiCH has a higher current leakage level under high bias and a lower breakdown field than silicon nitride.
In U.S. Pat. No. 6,436,824, a carbon doped silicon nitride layer with a dielectric constant of less than 3 is used as an etch stop layer. While SiCN can improve the leakage performance, trace amounts of amines in SiCN have a tendency to poison a photoresist layer in a via hole during patterning of a trench opening in a via first dual damascene scheme. Thus, a non-nitrogen containing etch stop layer is preferred.
In U.S. Pat. No. 6,528,116, a substrate is first treated with free atomic hydrogen to remove Al2O3 on an aluminum layer and then carbon doped SiO2 is deposited as a dielectric layer. A thermal process is preferred over a CVD or plasma enhanced CVD method to achieve a lower k value for the carbon doped SiO2 layer. In some applications, however, adhesion of the SiCOH dielectric layer to the substrate may suffer because of a lack of a barrier layer that functions as a glue layer.